1. Field of the Invention
The present invention relates to delay analysis processing of semiconductor integrated circuits, and in particular to delay analysis devices, delay analysis methods, and delay analysis programs, all of which perform delay analysis processing on semiconductor integrated circuits subsequently to chip layouts so as to reduce clock skews.
2. Description of the Related Art
Due to the rapid increase in the sizes of LSI chips, a high machine performance and a large memory capacity are needed to handle EDA (Electronic Design Automation) tools; hence, it becomes difficult to entirely process LSI chips at once. To cope with the rapid increase in the sizes of LSI chips, a dominant manufacturing method has been developed to design a single LSI chip in units of hierarchical subdivisions of the circuitry (referred to as “macros”). After a chip layout, a part of the circuitry (referred to as “an arbitrary region”) can be isolated from an LSI circuit and subjected to further processing. Since LSI chips are being rapidly developed to have high-speed performance, LSI chips serving as synchronization circuits, for example, need to secure concurrent operations among flip-flops (FF). In this case, it is important to reduce clock skews (i.e. significant differences of delay times between clock signals input to flip-flops) as low as possible. In the delay analysis processing on an arbitrary region of the hierarchical architecture of the circuitry or a part of the circuitry isolated from an LSI chip after a chip layout, it is necessary to remove design margins regarding clock skews (i.e. differences of delay times between clock signals) as much as possible. Due to the rapid increase in the sizes of LSI chips, a single LSI chip needs to be designed in units of macros in the hierarchical architecture of the circuitry. Alternatively, an arbitrary region of a single LSI chip is isolated and subjected to further processing subsequently to a chip layout.
FIG. 11 shows a clock distribution method in the hierarchical architecture of the circuitry, wherein clock distribution is performed in a top layout and a macro layout. A generally-known technique is to merge clock distribution of a top layout with clock distribution of a macro layout in further processing of chips. This clock distribution method suffers from a larger clock skew due to a large number of stages needed to establish synchronization on each chip entirely. Specifically, FIG. 11 shows that a clock path c1 bypasses a macro m1 and leads to a macro m2, while a clock path c2 bypasses the macro m1 and leads to a macro m3, wherein it needs a large number of stages (i.e. a large number of drivers), which in turn increases a clock skew due to wiring delays and driver delays.
Another clock distribution method is developed in light of the above drawback, wherein clock distribution is performed on the entire surface of an LSI chip in a top process, while a macro process is performed on a certain number of clock paths which are laid in a macro and which are extracted from clock paths distributed on the entire surface of an LSI chip, whereby the clock distribution of the macro process is performed such that drivers at distal ends of a clock tree are simply connected to flip-flops (FF) in the macro as shown in FIG. 12. Compared with the foregoing clock distribution method, this clock distribution method is able to reduce the number of stages of a clock tree and to thereby reduce a clock skew. Patent Document 1 discloses one relevant technology.                Patent Document 1: Japanese Patent Application Publication No. 2003-296387        Patent Document 2: Japanese Patent Application Publication No. 2001-273338        Patent Document 3: Japanese Patent Application Publication No. 2006-39621        Patent Document 4: Japanese Patent Application Publication No. 2000-259686        Patent Document 5: Japanese Patent Application Publication No. 2000-305966        Patent Document 6: Japanese Patent Application Publication No. 2000-250950        Patent Document 7: Japanese Patent Application Publication No. 2008-9787        Patent Document 8: Japanese Patent Application Publication No. 2005-235804        Patent Document 9: Japanese Patent Application Publication No. 2000-243846        Patent Document 10: Japanese Patent Application Publication No. 2000-223578        Patent Document 11: Japanese Patent Application Publication No. 2000-172738        Patent Document 12: Japanese Patent Application Publication No. 2000-100948        Patent Document 13: Japanese Patent Application Publication No. 2007-257293        Patent Document 14: Japanese Patent Application Publication No. 2005-284826        Patent Document 15: Japanese Patent Application Publication No. 2007-34668        Patent Document 16: Japanese Patent Application Publication No. 2000-242675        
In the clock distribution method of FIG. 12, a macro is isolated from an LSI chip having clock paths distributed on the entire surface and subjected to a macro process. When a macro is isolated without noticing the “physical” positional relationship of clock distribution, fragmentary clock paths whose clock terminals are laid in a macro boundary must be included in the macro being isolated from the LSI chip. In the macro process performed on a macro having fragmentary clock paths, it is difficult to adopt a high-precision clock skew in the macro delay analysis due to differences of clock paths having different numbers of stages included in clock trees, each of which leads from a clock source (PLL) of an LSI chip to clock terminals at a macro boundary. For this reason, it is necessary to adopt a large clock skew preventing an under-margined condition throughout an LSI chip; in other words, delay analysis must be performed based on an unnecessarily large clock skew, which is a bottleneck factor in terms of the optimum macro architecture of the circuitry. A similar drawback occurs when delay analysis is performed on an arbitrary region of the hierarchical architecture of the circuitry subsequently to a chip layout.